The present invention relates to electronic circuits, and more particularly to a dynamic flip-flop.
Flip-flops are widely used in electronic circuits to store and supply data. One type of flip-flop, commonly known as a dynamic flip-flop (DFF), operates differentially at relatively high speeds and consumes relatively low power. A DFF adapted to operate at a high speed, may have an excessive leakage current when operated at a relatively lower speed. The leakage may result in operational failure of the DFF.
FIG. 1 is a block diagram of a DFF 10, as known in the prior art. DFF 10 is shown as including a differential sense amplifier 100 and an SR latch 50. FIG. 2 is transistor schematic diagram of differential sense amplifier 100 of FIG. 1. Differential sense amplifier 100 includes a latch 150 adapted to store data. Accordingly, differential sense amplifier 100 is alternatively referred to hereinbelow as a latch.
Differential sense amplifier 100 is adapted to be reset when signal RSTN is at a low level and is adapted to store data when signal RSTN is at a high level and in response to the clock signal CLK. Assume signal RSTN is at a high level and signal CLK is at a low level. Accordingly, nodes RB and SB are charged to the supply voltage Vcc respectively via transistors 110, and 210. The high voltage at node SB causes node SB1 to be charged to voltage (Vcc-Vth), where Vth is the threshold voltage of any of the NMOS transistors shown in FIG. 2. Similarly, the high voltage at node RB causes node RB1 to be charged to voltage (Vcc-Vth).
Assume that the data supplied to terminal D is at a high level, i.e., logic level 1, when clock signal CLK transitions from low to high. This transition causes node SB1 to be pulled to the Vss potential via transistors 116, 128 and 130. Because the data supplied to terminal DB is the inverse of that supplied to terminal D, node RB1 remains at its previous high voltage. The low voltage at node SB1 also enables the voltage at node SB to be pulled to the Vss potential via transistor 114. Accordingly, when the clock signal switches from low to high, if terminals D and DB are at high and low voltage levels respectively, node SB is discharged to the Vss potential. Transistors 112, 114, 212 and 214 form a latch 150 adapted to maintain nodes SB and RB at their respective low and high values.
Inversely, when the clock signal switches from low to high, if terminals D and DB are at low and high voltage levels respectively, node RB is discharged to the Vss potential, whereas node SB is maintained at the Vcc potential. Latch 150 maintains nodes SB and RB at their respective high and low values.
Assume latch 150 is set such that nodes SB and RB are respectively at low and high values. Assume after latch 150 is set and while clock signal CLK is active high, data input terminal D switches to a low level. Accordingly, transistor 116 is turned off thus causing node SB1 and SB to float. When differential sense amplifier 100 operates at a low clock frequency, node SB may be charged to the Vcc potential via transistors 102, 110 and 112, causing DFF 100 to switch state, thereby resulting in operational failure of sense amplifier 100.